Design, implementation and testing of the controller for the terabit packet switch
Abstract
The sequential greedy scheduling (SGS) is a scalable algorithm that provides non-blocking in high-capacity packet switches. We implemented the SGS scheduler in the FPGA device, and examined its scalability and speed. Then, we developed the software for design testing. Our testing software confirms the correct functioning of the scheduler. Both, the scheduler implementation, and the testing software are presented in this paper.
Source:
2006 International Conference on Communications, Circuits and Systems Proceedings, Vols 1-4: Vol 1:, 2006, 1701-+Publisher:
- IEEE, New York
Funding / projects:
- Ministry of Science
- Environmental Protection of the Republic of Serbia
- Pupin Telecom DKTS.
DOI: 10.1109/ICCCAS.2006.285001
ISBN: 0780395840
WoS: 000241262902056
Scopus: 2-s2.0-39749101129
Institution/Community
Tehnološko-metalurški fakultetTY - CONF AU - Petrović, Miloš AU - Blagojević, Miloš AU - Smiljanić, Aleksandra AU - Joković, Vladimir PY - 2006 UR - http://TechnoRep.tmf.bg.ac.rs/handle/123456789/904 AB - The sequential greedy scheduling (SGS) is a scalable algorithm that provides non-blocking in high-capacity packet switches. We implemented the SGS scheduler in the FPGA device, and examined its scalability and speed. Then, we developed the software for design testing. Our testing software confirms the correct functioning of the scheduler. Both, the scheduler implementation, and the testing software are presented in this paper. PB - IEEE, New York C3 - 2006 International Conference on Communications, Circuits and Systems Proceedings, Vols 1-4: Vol 1: T1 - Design, implementation and testing of the controller for the terabit packet switch EP - + SP - 1701 DO - 10.1109/ICCCAS.2006.285001 ER -
@conference{ author = "Petrović, Miloš and Blagojević, Miloš and Smiljanić, Aleksandra and Joković, Vladimir", year = "2006", abstract = "The sequential greedy scheduling (SGS) is a scalable algorithm that provides non-blocking in high-capacity packet switches. We implemented the SGS scheduler in the FPGA device, and examined its scalability and speed. Then, we developed the software for design testing. Our testing software confirms the correct functioning of the scheduler. Both, the scheduler implementation, and the testing software are presented in this paper.", publisher = "IEEE, New York", journal = "2006 International Conference on Communications, Circuits and Systems Proceedings, Vols 1-4: Vol 1:", title = "Design, implementation and testing of the controller for the terabit packet switch", pages = "+-1701", doi = "10.1109/ICCCAS.2006.285001" }
Petrović, M., Blagojević, M., Smiljanić, A.,& Joković, V.. (2006). Design, implementation and testing of the controller for the terabit packet switch. in 2006 International Conference on Communications, Circuits and Systems Proceedings, Vols 1-4: Vol 1: IEEE, New York., 1701-+. https://doi.org/10.1109/ICCCAS.2006.285001
Petrović M, Blagojević M, Smiljanić A, Joković V. Design, implementation and testing of the controller for the terabit packet switch. in 2006 International Conference on Communications, Circuits and Systems Proceedings, Vols 1-4: Vol 1:. 2006;:1701-+. doi:10.1109/ICCCAS.2006.285001 .
Petrović, Miloš, Blagojević, Miloš, Smiljanić, Aleksandra, Joković, Vladimir, "Design, implementation and testing of the controller for the terabit packet switch" in 2006 International Conference on Communications, Circuits and Systems Proceedings, Vols 1-4: Vol 1: (2006):1701-+, https://doi.org/10.1109/ICCCAS.2006.285001 . .