Optimization of the scheduler for the non-blocking high-capacity router
Само за регистроване кориснике
2007
Чланак у часопису (Објављена верзија)
Метаподаци
Приказ свих података о документуАпстракт
The sequential greedy scheduling (SGS) is a scalable maximal matching algorithm that provides non-blocking in an Internet router with input buffers and a cross-bar. In this paper, we will present the FPGA design of the SGS scheduler. We have optimized scheduler components, and we will prove their correct functioning. The scheduler optimization significantly reduces the worst-case packet delay through the router.
Кључне речи:
packet switches / scheduling / high-performance / FPGA / circuit optimizationИзвор:
IEEE Communications Letters, 2007, 11, 6, 534-536Издавач:
- IEEE-Inst Electrical Electronics Engineers Inc, Piscataway
DOI: 10.1109/LCOMM.2007.061653
ISSN: 1089-7798
WoS: 000247223300024
Scopus: 2-s2.0-34548031355
Институција/група
Tehnološko-metalurški fakultetTY - JOUR AU - Petrović, Miloš AU - Smiljanić, Aleksandra PY - 2007 UR - http://TechnoRep.tmf.bg.ac.rs/handle/123456789/1086 AB - The sequential greedy scheduling (SGS) is a scalable maximal matching algorithm that provides non-blocking in an Internet router with input buffers and a cross-bar. In this paper, we will present the FPGA design of the SGS scheduler. We have optimized scheduler components, and we will prove their correct functioning. The scheduler optimization significantly reduces the worst-case packet delay through the router. PB - IEEE-Inst Electrical Electronics Engineers Inc, Piscataway T2 - IEEE Communications Letters T1 - Optimization of the scheduler for the non-blocking high-capacity router EP - 536 IS - 6 SP - 534 VL - 11 DO - 10.1109/LCOMM.2007.061653 ER -
@article{ author = "Petrović, Miloš and Smiljanić, Aleksandra", year = "2007", abstract = "The sequential greedy scheduling (SGS) is a scalable maximal matching algorithm that provides non-blocking in an Internet router with input buffers and a cross-bar. In this paper, we will present the FPGA design of the SGS scheduler. We have optimized scheduler components, and we will prove their correct functioning. The scheduler optimization significantly reduces the worst-case packet delay through the router.", publisher = "IEEE-Inst Electrical Electronics Engineers Inc, Piscataway", journal = "IEEE Communications Letters", title = "Optimization of the scheduler for the non-blocking high-capacity router", pages = "536-534", number = "6", volume = "11", doi = "10.1109/LCOMM.2007.061653" }
Petrović, M.,& Smiljanić, A.. (2007). Optimization of the scheduler for the non-blocking high-capacity router. in IEEE Communications Letters IEEE-Inst Electrical Electronics Engineers Inc, Piscataway., 11(6), 534-536. https://doi.org/10.1109/LCOMM.2007.061653
Petrović M, Smiljanić A. Optimization of the scheduler for the non-blocking high-capacity router. in IEEE Communications Letters. 2007;11(6):534-536. doi:10.1109/LCOMM.2007.061653 .
Petrović, Miloš, Smiljanić, Aleksandra, "Optimization of the scheduler for the non-blocking high-capacity router" in IEEE Communications Letters, 11, no. 6 (2007):534-536, https://doi.org/10.1109/LCOMM.2007.061653 . .