Design of the Switching Controller for the High-Capacity Non-Blocking Internet Router
Само за регистроване кориснике
2009
Чланак у часопису (Објављена верзија)
Метаподаци
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The sequential greedy scheduling (SGS) algorithm is a scalable maximal matching algorithm. This algorithm was conceptually proposed and well received since it provides non-blocking in an Internet router with input buffers and a cross-bar, unlike other existing implementations. In this paper, we implent a new design of the SGS algorithm, and determine its exact behaviour, performance and QoS that it provides. We examine different design options and measure the performance of their implementations in terms of their scalability and speed. It will be shown that multiple scheduler modules of a terabit Internet router can be implemented on a low-cost field-programmable gate-array (FPGA) device, and that the processing can be performed within the desired time slot duration. Proper functioning of the implemented scheduler was confirmed through thorough software and hardware testing.
Кључне речи:
Field-programmable gate-array (FPGA) implementation / high-capacity / non-blocking / packet switchingИзвор:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2009, 17, 8, 1157-1161Издавач:
- IEEE-Inst Electrical Electronics Engineers Inc, Piscataway
Финансирање / пројекти:
- Ministry of Science and Enviromental Protection of the Republic of Serbia
- Pupin Telecom DKTS
DOI: 10.1109/TVLSI.2009.2019817
ISSN: 1063-8210
WoS: 000268282700018
Scopus: 2-s2.0-68549128547
Институција/група
Tehnološko-metalurški fakultetTY - JOUR AU - Petrović, Miloš AU - Smiljanić, Aleksandra AU - Blagojević, Miloš PY - 2009 UR - http://TechnoRep.tmf.bg.ac.rs/handle/123456789/1433 AB - The sequential greedy scheduling (SGS) algorithm is a scalable maximal matching algorithm. This algorithm was conceptually proposed and well received since it provides non-blocking in an Internet router with input buffers and a cross-bar, unlike other existing implementations. In this paper, we implent a new design of the SGS algorithm, and determine its exact behaviour, performance and QoS that it provides. We examine different design options and measure the performance of their implementations in terms of their scalability and speed. It will be shown that multiple scheduler modules of a terabit Internet router can be implemented on a low-cost field-programmable gate-array (FPGA) device, and that the processing can be performed within the desired time slot duration. Proper functioning of the implemented scheduler was confirmed through thorough software and hardware testing. PB - IEEE-Inst Electrical Electronics Engineers Inc, Piscataway T2 - IEEE Transactions on Very Large Scale Integration (VLSI) Systems T1 - Design of the Switching Controller for the High-Capacity Non-Blocking Internet Router EP - 1161 IS - 8 SP - 1157 VL - 17 DO - 10.1109/TVLSI.2009.2019817 ER -
@article{ author = "Petrović, Miloš and Smiljanić, Aleksandra and Blagojević, Miloš", year = "2009", abstract = "The sequential greedy scheduling (SGS) algorithm is a scalable maximal matching algorithm. This algorithm was conceptually proposed and well received since it provides non-blocking in an Internet router with input buffers and a cross-bar, unlike other existing implementations. In this paper, we implent a new design of the SGS algorithm, and determine its exact behaviour, performance and QoS that it provides. We examine different design options and measure the performance of their implementations in terms of their scalability and speed. It will be shown that multiple scheduler modules of a terabit Internet router can be implemented on a low-cost field-programmable gate-array (FPGA) device, and that the processing can be performed within the desired time slot duration. Proper functioning of the implemented scheduler was confirmed through thorough software and hardware testing.", publisher = "IEEE-Inst Electrical Electronics Engineers Inc, Piscataway", journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems", title = "Design of the Switching Controller for the High-Capacity Non-Blocking Internet Router", pages = "1161-1157", number = "8", volume = "17", doi = "10.1109/TVLSI.2009.2019817" }
Petrović, M., Smiljanić, A.,& Blagojević, M.. (2009). Design of the Switching Controller for the High-Capacity Non-Blocking Internet Router. in IEEE Transactions on Very Large Scale Integration (VLSI) Systems IEEE-Inst Electrical Electronics Engineers Inc, Piscataway., 17(8), 1157-1161. https://doi.org/10.1109/TVLSI.2009.2019817
Petrović M, Smiljanić A, Blagojević M. Design of the Switching Controller for the High-Capacity Non-Blocking Internet Router. in IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2009;17(8):1157-1161. doi:10.1109/TVLSI.2009.2019817 .
Petrović, Miloš, Smiljanić, Aleksandra, Blagojević, Miloš, "Design of the Switching Controller for the High-Capacity Non-Blocking Internet Router" in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17, no. 8 (2009):1157-1161, https://doi.org/10.1109/TVLSI.2009.2019817 . .