Design, implementation and testing of the controller for the terabit packet switch

dc.creator	Petrović, Miloš
dc.creator	Blagojević, Miloš
dc.creator	Smiljanić, Aleksandra
dc.creator	Joković, Vladimir
dc.date.accessioned	2021-03-10T10:31:19Z
dc.date.available	2021-03-10T10:31:19Z
dc.date.issued	2006
dc.identifier.isbn	0780395840
dc.identifier.uri	http://TechnoRep.tmf.bg.ac.rs/handle/123456789/904
dc.description.abstract	The sequential greedy scheduling (SGS) is a scalable algorithm that provides non-blocking in high-capacity packet switches. We implemented the SGS scheduler in the FPGA device, and examined its scalability and speed. Then, we developed the software for design testing. Our testing software confirms the correct functioning of the scheduler. Both, the scheduler implementation, and the testing software are presented in this paper.	en
dc.publisher	IEEE, New York
dc.relation	Ministry of Science
dc.relation	Environmental Protection of the Republic of Serbia
dc.relation	Pupin Telecom DKTS.
dc.rights	restrictedAccess
dc.source	2006 International Conference on Communications, Circuits and Systems Proceedings, Vols 1-4: Vol 1:
dc.title	Design, implementation and testing of the controller for the terabit packet switch	en
dc.type	conferenceObject
dc.rights.license	ARR
dc.citation.epage	+
dc.citation.other	: 1701-+
dc.citation.spage	1701
dc.identifier.doi	10.1109/ICCCAS.2006.285001
dc.identifier.scopus	2-s2.0-39749101129
dc.identifier.wos	000241262902056
dc.type.version	publishedVersion