Design of the scheduler for the high-capacity non-blocking packet switch
Abstract
The sequential greedy scheduling (SGS) is a scalable maximal matching algorithm that provides non-blocking in a packet switch with input buffers and a cross-bar. In this paper, we propose the design of the SGS scheduler, and present its FPGA implementation. We examine different design options and measure these implementations in terms of their scalability and speed. It will be shown that multiple input modules of a terabit packet switch can be implemented on one low-cost FPGA device and that the processing can be performed within desired time slot duration.
Source:
HPSR: 2006 Workshop on High Performance Switching and Routing, 2006, 397-402Publisher:
- IEEE, New York
Institution/Community
Tehnološko-metalurški fakultetTY - CONF AU - Petrović, Miloš AU - Smiljanić, Aleksandra PY - 2006 UR - http://TechnoRep.tmf.bg.ac.rs/handle/123456789/962 AB - The sequential greedy scheduling (SGS) is a scalable maximal matching algorithm that provides non-blocking in a packet switch with input buffers and a cross-bar. In this paper, we propose the design of the SGS scheduler, and present its FPGA implementation. We examine different design options and measure these implementations in terms of their scalability and speed. It will be shown that multiple input modules of a terabit packet switch can be implemented on one low-cost FPGA device and that the processing can be performed within desired time slot duration. PB - IEEE, New York C3 - HPSR: 2006 Workshop on High Performance Switching and Routing T1 - Design of the scheduler for the high-capacity non-blocking packet switch EP - 402 SP - 397 UR - https://hdl.handle.net/21.15107/rcub_technorep_962 ER -
@conference{ author = "Petrović, Miloš and Smiljanić, Aleksandra", year = "2006", abstract = "The sequential greedy scheduling (SGS) is a scalable maximal matching algorithm that provides non-blocking in a packet switch with input buffers and a cross-bar. In this paper, we propose the design of the SGS scheduler, and present its FPGA implementation. We examine different design options and measure these implementations in terms of their scalability and speed. It will be shown that multiple input modules of a terabit packet switch can be implemented on one low-cost FPGA device and that the processing can be performed within desired time slot duration.", publisher = "IEEE, New York", journal = "HPSR: 2006 Workshop on High Performance Switching and Routing", title = "Design of the scheduler for the high-capacity non-blocking packet switch", pages = "402-397", url = "https://hdl.handle.net/21.15107/rcub_technorep_962" }
Petrović, M.,& Smiljanić, A.. (2006). Design of the scheduler for the high-capacity non-blocking packet switch. in HPSR: 2006 Workshop on High Performance Switching and Routing IEEE, New York., 397-402. https://hdl.handle.net/21.15107/rcub_technorep_962
Petrović M, Smiljanić A. Design of the scheduler for the high-capacity non-blocking packet switch. in HPSR: 2006 Workshop on High Performance Switching and Routing. 2006;:397-402. https://hdl.handle.net/21.15107/rcub_technorep_962 .
Petrović, Miloš, Smiljanić, Aleksandra, "Design of the scheduler for the high-capacity non-blocking packet switch" in HPSR: 2006 Workshop on High Performance Switching and Routing (2006):397-402, https://hdl.handle.net/21.15107/rcub_technorep_962 .